The present invention relates to a microprogram memory output circuit and, in particular, to a microprogram memory output circuit in verification of data within the microprogram memory of a semiconductor integrated circuit.
A circuit for generating microinstructions stored with a conventional microprogram memory to the external output terminals is described with reference to the block diagram of FIG. 1. The circuit comprises a microprogram ROM 101 (hereinafter referred to as MROM) having a 48-bit long microinstruction word, a bus selector 107 taking a MROM data bus MD bit (47 to 40) field signal 211 from the MROM 101, MROM data bus MD bit (39 to 32) field signal 212, a MROM data bus MD bit (31 to 24) field signal 213, a MROM data bus MD bit (23 to 16) field signal 214, a MROM data bus MD bit (15 to 8) field signal 215 and a MROM data bus MD bit (7 to 0) field signal 216 as its inputs, a bus selector/address controller 104a for controlling the MROM 101 and the bus selector 107 and an output circuit 108 for transferring the output of the bus selector 107 to the 8-bit long external output terminal 210.
MROM 101 divides the 48-bit long microinstruction selected at MROM address 301, which is entered from bus selector/address controller 104a, into six fields: microinstruction word bits (47 to 40), (39 to 32), (31 to 24), (23 to 16), (15 to 8) and (7 to 0) to generate each bit field of the microinstruction word to the MROM data bus MD bit (47 to 40), (39 to 32), (31 to 24), (23 to 16), (15 to 8) and (7 to 0) field signals 211 through 216 respectively.
FIG. 2 illustrates a block diagram of the bus selector/address controller 104a, which comprises an address generator 110 and a control signal generating unit 111a.
The address generator 110 comprises address incrementing means for incrementing one by one for each clock, means for generating an MROM address to generate as the MROM address 301 and means for generating a carry signal 304 when any carry over takes place from the most significant bit of the MROM address 301. The carry signal 304 is supplied as the trigger signal addressed to the control signal generating unit 111a. When a reset signal 305 becomes effective, the address generator 110 is reset and the MROM address 301 is initialized.
The control signal generating unit 111a has a 3-bit long combination circuit 113, and uses the output of this 3-bit long combination circuit 113 as the bus selector control signal 306.
The 3-bit long combination circuit 113 is initialized to the value "000" when the reset signal 305 becomes effective to sequentially generate the codes "001", "010", "011", "100" and "101" as the bus selector control signal 306 with the carry signal 304 from the address generator 110 as the trigger.
The bus selector 106, as shown in FIG. 3, comprises a local data bus multiplexer 131 and a bus selector control signal decoder 132. The entered field signals 211 through 216 of MROM data bus MD bits (47 to 40), (39 to 32), (31 to 24), (23 to 16), (15 to 8) and (7 to 0) are selected by the bus selector control signal 306 to be generated to a local data bus 207, in which, when the bus selector control signal 306 takes the code "000", the MROM data bus MD bit (47 to 40) field signal 211 is selected, and when it takes the code "001", "010", "011""100", and "101", the MROM data bus MD bit field signals 212 through 216 are each respectively selected. Further, the output means 106 serves to generate the microinstruction word on the local data bus 207 to the external output terminal 210 in synchronism with the external clock signal.
When the reset signal becomes effective, the bus selector/address controller 104a is initialized, and the bus selector 107, in synchronism with the external clock, generates the MROM data bus MD bit (47 to 40) field signal 211 to the local data bus 207. The carry signal 304 resulting from the carryover from the most significant bit of the MROM address 301 causes the bus selector 107 to sequentially generate each field signal 212 through 216 of the MROM data bus MD bit to the local data bus 207 respectively. Therefore, reading of the microinstruction word in synchronism with the external clock may cause all the microinstruction words stored within the MROM to be generated to the external output terminal.
Due to the diversification and the cost reduction of the semiconductor integrated circuit, a microprocessor has been called for which may generate the microinstruction word stored within the microprogram memory to be generated to the external output terminal of different length, for example, 16 or 32-bit external data bus terminal.
The foregoing conventional circuit can cope with the foregoing task, if the microinstruction word is divided into below the bit length of the external output terminal and the circuit is changed in accordance with the bus selector 107, bus selector/address controller 104a and the divided microinstruction word.
However, since a microprocessor must be manufactured for each external output terminal of a different bit length, extra manufacturing time is required which exerts an adverse effect on the cost reduction.
Therefore, an object of the present invention is to eliminate these problems and to provide a novel microprogram memory output circuit which allows the microinstruction word to be selectively generated to output terminals of different bit lengths.